A pipelined ADC is shown generally at 20 in FIG. 1. A pipelined ADC typically includes an input sample and hold amplifier circuit (SHA) 22 and several pipeline stages 23, 25 and 27. Each pipeline stage generally comprises a flash analog-to-digital converter (flash ADC) such as 30, 32, 34 and 36 and a corresponding residue amplifier 24, 26 and 28. Each residue amplifier 24, 26 and 28, in turn, includes at least one amplifier stage, a digital-to-analog converter (DAC), as well as a SHA. The interrelationship among these components is explained below.
The SHA 22 samples a signal at the input of the pipelined ADC 20, VIN, and holds this signal at its output long enough to allow a first stage 23 of the pipeline to operate on it. This first stage 23 includes a first-stage flash ADC 30 and a first-stage residue amplifier 24. The first-stage flash ADC 30 quantizes the sampled signal and provides an n-bit digital word. This word represents the amplitude of the sampled signal (relative to the flash ADC reference voltage), accurate to n-bits. The first-stage DAC (within residue amplifier 24) then accepts the n-bit word from the first-stage flash ADC 30 and converts the word back into analog format. The first-stage residue amplifier 24 measures the amplitude difference between the sampled signal and the n-bit approximation of the sample as supplied by the first-stage DAC (within residue amplifier 24). This difference is termed the first-stage "residue," as it represents the portion of the signal beyond the resolution of the first n-bit conversion. The first-stage residue amplifier 24 then amplifies the first-stage residue by a factor of 2.sup.n, and holds the amplified first-stage residue while it is processed in the second stage 25 of the pipeline.
In the second pipeline stage 25, a second-stage flash ADC 32 quantizes the amplified first-stage residue into an m-bit digital word, i.e., a word accurate to m-bits. A second-stage DAC (within residue amplifier 26) converts the m-bit digital word back into analog format, and the second-stage residue amplifier 26 measures the difference between the actual amplified residue from the first-stage residue amplifier 24 and the analog output of the second-stage DAC (within residue amplifier 26). This difference represents the residue from the second-stage flash ADC 32 and is further amplified by a factor of 2.sup.m to provide an amplified second-stage residue. This amplified second-stage residue then is held by the second-stage residue amplifier 26 while it is processed in the following stage of the pipeline. This process may be continued with additional pipeline stages as required to achieve the desired resolution. A digital adder 38 combines the outputs of flash ADCs 30, 32, 34 and 36 and provides a digital output to output bus 40.
Thus, after the first two pipeline stages, an (m+n) bit digital word (accurate to (m+n) bits) is obtained. In other words, the first stage provides a rough measurement of the sampled signal (accurate to a finite number of bits), and each successive stage fine-tunes that measurement. In many practical implementations, an amplification factor of less than 2.sup.n in the first stage and less than 2.sup.m in the second stage is implemented so that some form of digital correction can be used to correct errors in the flash ADCs. For example, many pipeline converters manufactured today are implemented with residue amplification factors of 2.sup.n-1 and 2.sup.m-1 respectively in the first and second stage residue amplifiers, and provide an m+n-1 bit digital word accurate to m+n-1 bits after the first two pipeline stages.
It is apparent from the foregoing that the proper design of the residue amplifiers 24, 26 and 28 is of particular relevance in maximizing the speed and accuracy of a pipelined ADC. Traditionally, pipelined ADCs have employed high-speed switched-capacitor circuits as residue amplifiers. Such switched-capacitor circuits normally use single-stage amplifier structures to achieve fast settling times. To attain high gain with these devices, cascode transistors commonly are used in their Outputs to increase the output impedance of the amplifiers, thereby increasing their gain. An example of a prior art single-stage cascode circuit, commonly referred to as a "telescopic" cascode amplifier, is shown at 41 in FIG. 2. In this example, the circuit of amplifier 41 is cascoded twice (with cascode transistors M4-M7) to achieve twice the cascode gain in the one stage than a single cascode transistor would provide. The open-loop bandwidth of such a single-stage device (OLBW.sub.(SINGLE-STAGE)) is defined by the transconductance (gm) of the single-stage amplifier divided by the capacitance loading the output (C.sub.L), i.e., OLBW.sub.(SINGLE-STAGE) =gm/C.sub.L. Such a single-stage amplifier circuit also has a non-dominant parasitic pole at a frequency dictated by the parasitic capacitances of the MOS transistors in the signal path of the amplifier. Since the frequency location of this parasitic pole can be optimized to be as large as one giga-hertz (GHz). the closed-loop bandwidth of a single-stage amplifier may be increased to nearly this value before the phase margin of the circuit degrades (due to the non-dominant pole) and causes the circuit to become unstable. Thus, by utilizing proper gain enhancement techniques (e.g., telescopic cascodes), a single-stage amplifier circuit can be made to settle quickly.
There, however, are several drawbacks associated with single-stage telescopic cascodes. First, telescopic cascode amplifiers are not well suited for use with large capacitive loads. Because the open-loop bandwidth of a single-stage amplifier (OLBW.sub.(SINGLE-STAGE)) is determined by dividing the input transconductance (gm) by the output load capacitance (C.sub.L), i.e., OLBW.sub.(SINGLE-STAGE) =gm/C.sub.L, to maintain a high bandwidth in a circuit with a large capacitive load, a large gm is required to counteract the large capacitance value of C.sub.L. One way to increase the transconductance of an amplifier is to use larger transistors in the amplifier's signal path. Normally, a single-stage amplifier will have a feedback capacitance (C.sub.F) connected between its output and its input, and will have an input capacitance (C.sub.IN) connected to its input to be charged by an input signal. There also may be a parasitic capacitance (C.sub.P) (from the intrinsic properties of the MOS input transistors) at the input of the amplifier. The feedback attenuation (ATTEN.sub.FB) of such a circuit is determined by the following equation: ATTEN.sub.FB =C.sub.F /(C.sub.F +C.sub.IN +C.sub.P). Therefore, the closed-loop bandwidth of the single-stage circuit (CLBW.sub.(SINGLE-STAGE)) is determined by multiplying the open-loop bandwidth (OLBW.sub.(SINGLE-STAGE)) by the feedback attenuation (ATTEN.sub.FB), i.e. CLBW.sub.(SINGLE-STAGE) =OLBW.sub.(SINGLE-STAGE) * ATTEN.sub.FB =(gm/C.sub.L) * C.sub.F /(C.sub.F +C.sub.IN +C.sub.P), where * indicates multiplication.
The transconductance may be raised (to counteract a large capacitance value of C.sub.L) by increasing the transistor sizes, but a large increase in the transistor sizes will result in a substantial increase in the parasitic capacitance (C.sub.P) at the input. This increase in the parasitic capacitance may, in turn, substantially decrease the closed-loop bandwidth of the amplifier circuit through feedback attenuation. Thus, an upper limit is placed on the amount the transconductance may be increased (by increasing the transistor size) without having the increased parasitic capacitance limit the bandwidth.
Another way to increase the input transconductance (gm) of a single-stage amplifier is to use mirror gain. This is accomplished by mirroring the current provided at the output of the input transistors (i.e., the input current multiplied by the value of gm) to the cascode output structure. By doing this, the effective transconductance of the amplifier is made equal to the transistor transconductance (gm) multiplied by the current gain of the current mirror. The drawback to using mirror gain, however, is that the current mirror adds parasitic capacitance in the signal path. Also, such a mirrored circuit has a unique noise disadvantage caused by using an inherently smaller gm in conjunction with an intentionally increased bandwidth.
The second problem with a telescopic cascode amplifier is that it imposes a severe headroom constraint on the output signal swing capability. Since each cascode transistor must have a drain-to-source voltage (V.sub.DS) of at least its gate-to-source voltage (V.sub.GS) minus its threshold voltage (V.sub.T), i.e., V.sub.DS &gt;V.sub.GS -V.sub.T, multiple cascode devices arranged in series (when biased correctly) require a significant voltage drop across them, thereby substantially reducing the voltage swing headroom available at the output of the amplifier. This especially becomes a problem when the amplifier is operating from limited voltage rails (e.g.. three volts).
An alternative to using a single-stage amplifier is to use a two-stage amplifier with Miller compensation, i.e., a Miller capacitance (C.sub.C) coupled between the second-stage output and the second-stage input. By using such a structure, the overall gain requirement may be spread over the two-stages so that minimum channel length transistors may be used in each stage. Additionally, because all of the gain need not be achieved in a single stage (requiring multiple cascode transistors), the use of two stages alleviates the lack of output signal swing headroom that was encountered with the use of a single-stage amplifier circuit.
The bandwidth of a Miller-compensated two-stage amplifier (BW.sub.(TWO-STAGE)) is determined by dividing the transconductance of the first stage (gm1) by the Miller capacitance (C.sub.C), i.e., BW.sub.(TWO-STAGE) =gm1/C.sub.C. Thus, the bandwidth can be somewhat controlled by appropriately selecting the value of the Miller capacitance (C.sub.C). A two-stage structure also has a non-dominant pole (P2) at a frequency location determined by the following equation: P2.congruent.(gm2/C.sub.L) * C.sub.C /(C.sub.C +C.sub.P2), where gm2 is the transconductance of the second state and C.sub.P2 is the parasitic capacitance at the input of the second stage. Additionally, a two-stage amplifier has a third non-dominant pole (P3) with a location dictated by the parasitic capacitances of the MOS transistors in the signal path of the amplifier. The location of this parasitic pole may be optimized to be at a very large frequency, i.e., approximately one GHz. As the signal frequency approaches the frequency of the first non-dominant pole (P2), however, the phase margin will degrade rapidly and the circuit will become unstable. Thus, although the bandwidth of the two-stage circuit may be increased (by increasing gm1 or by decreasing C.sub.C), the presence of pole P2 severely restricts the extension of the bandwidth beyond the location of pole P2.
FIG. 3 shows a prior art two-stage amplifier circuit 42 with a p-channel differential pair of transistors M1 and M2 as an input stage and an n-channel (single-ended) output-stage transistor M3. It is known that n-channel MOS transistors provide significantly more transconductance in relation to their size than do p-channel transistors. Typically, an n-channel device will provide a transconductance value that is approximately a factor of three greater than that of an equivalently sized p-channel device. The parasitic capacitances of p-channel and n-channel transistors, however, are nearly equal for equivalently sized devices. In view of the equation stated above regarding the location of pole P2, it is advantageous, then, to have an n-channel second stage (so as to optimize the location of pole P2).
Since each of the amplifying transistors must be biased so that its drain-to-source voltage (V.sub.DS) is greater than its gate-to-source voltage (V.sub.GS) minus a transistor threshold voltage (V.sub.T), i.e., V.sub.DS &gt;V.sub.GS -V.sub.T, it also makes sense that the input and output stages be transistors of opposite doping types, i.e., n-channel and p-channel. That is, given a limited supply voltage, it is much easier to bias the two stages of transistors when the input and output stages use oppositely doped transistors. This is especially true when the supply rails carry only about three volts.
In addition, the (larger) p-channel transistors are preferred in the first stage of a two-stage amplifier for a variety of reasons, including: (1) providing better matching between the transistors comprising a differential pair of input transistors, thereby reducing offset errors caused by mismatches between the pair, and (2) having lower "flicker noise," i.e., low frequency noise caused by trapped defects in the oxide layers or the substrates of the devices. Thus, the prior art teaches that in a limited headroom environment, although p-channel transistors have a larger parasitic capacitance (for an equivalent gain) than do n-channel transistors, it is a better design choice to use p-channel transistors in the first stage of a two-stage Miller-compensated amplifier.
Therefore, a need exists for an amplifier circuit suitable for use switched capacitor circuits that operate at very high frequencies.